The invention relates to a user-adjustable capacitor array that is manufacturer-trimmable to compensate for variations in absolute capacitance values, and more particularly to such a capacitor array which can be implemented in an integrated circuit using a minimum number of elements, and more particularly to such a capacitor array used as an integrating capacitor in a front-end integrator to an analog-to-digital converter, such as a delta-sigma analog-to-digital converter.
There are various applications in which a user-adjustable integrated circuit capacitor is needed. For example, in the front-end integrator to an analog-to-digital converter it may be desirable to have user-adjustable gain. The absolute value of the integration capacitor (rather than a ratio of capacitances) sets the overall gain of the circuit including the front-end integrator and the analog-to-digital converter. Unfortunately, the value of capacitance per unit area in ordinary integrated circuit manufacturing processes is usually not well controlled. Therefore, if an accurate value of capacitance is needed for an integrated circuit capacitor, the manufacturer must "trim" the capacitor as needed to compensate for the large variations inherent in ordinary integrated circuit manufacturing processes.
One well known way of trimming the value of an integrated circuit capacitor is to provide an array in which a main capacitor of somewhat smaller than "nominal" capacitance is initially in parallel with a number of smaller "trim" capacitors, which then can be removed from parallel connection with the main capacitor by "trimming", for example by using a laser to cut electrical connections which directly or indirectly remove one or more of the trim capacitors from parallel connection to the main capacitor. This technique has the significant drawback that it always requires that there be a capacitor trimming operation, even if the integrated circuit manufacturing process succeeds in providing exactly the desired or nominal capacitance per unit area of the integrated capacitors. This adds considerable unnecessary expense if the manufacturing process frequently succeeds in achieving "on target" capacitance per unit area. Another problem of this technique is that it is not well suited to use in a user-adjustable capacitor array because each user-adjustable capacitance value has to be separately trimmed.
U.S. Pat. No. 5,258,760 (Moody et al.) discloses a programmable integrator including both a programmable capacitor array and a programmable resistive voltage divider connected in series to form the integrating feedback element. This reference teaches that the provision of a dual-programmable feature permits a calibration adjustment of the integrator constant to compensate for component parameter variations in the resistance of a polycrystaline silicon integrating resistor. This approach to a programmable integrator adds considerable complexity and chip area to the integrator, and undesirably requires the operational amplifier to drive the programmable voltage divider.
It would be desirable to provide an improved integrated circuit capacitor array in which a desired absolute value of capacitance can be selected to appear between two terminals by a digital capacitance selection code, irrespective of deviations from nominal of the capacitance per unit area of the capacitors in the array.